1. Field of the Invention
The present invention relates to a display control circuit which is applied to a flat display panel such as a liquid crystal display panel.
2. Description of the Related Art
Flat-panel display devices, which are represented by liquid crystal display devices, are widely used in order to display images on personal computers, TV receivers, car navigation systems, etc.
A typical liquid crystal display device includes a liquid crystal display panel in which a plurality of liquid crystal pixels are arrayed in a matrix, and a display control circuit which controls the liquid crystal display panel (see, for instance, Jpn. Pat. Appln. KOKAI Publication No. 2002-196723). A typical liquid crystal display panel has a structure wherein a liquid crystal layer is held between an array substrate and a counter-substrate. The array substrate includes a plurality of pixel electrodes arrayed in a matrix, a plurality of gate lines (or scan lines) which are arranged along the rows of pixel electrodes, a plurality of source lines (or signal lines) arranged along the columns of pixel electrodes, and a plurality of switching elements disposed near intersections between the gate lines and source lines and connect, when the associated gate lines are driven, the associated source lines to the associated pixel electrodes. The counter-substrate includes a common electrode opposed to the pixel electrodes disposed on the array substrate. Each pixel electrode and the common electrode, together with a pixel region that is a part of the liquid crystal layer held between these electrodes, constitute a liquid crystal pixel and control the alignment of liquid crystal molecules in the pixel region by an electric field which corresponds to a liquid crystal driving voltage obtained as a potential difference between the pixel electrode and the common electrode.
The display control circuit includes a driver circuit which drives the liquid crystal pixels, and a driver control circuit which controls the driver circuit. The driver control circuit holds pixel data items which are cyclically extracted as a digital image signal from a video signal supplied from outside, and sets, e.g. the sequential order, resolution, gamma correction amount and display timing of the pixel data items to be suited for the liquid crystal display panel, thereby controlling the driver circuit. The driver circuit includes a gate driver which drives the gate lines so as to sequentially select the rows of pixels, and a source driver which digital-to-analog (D/A) converts the pixel data items for the pixels of a selected row, to pixel voltages and drives the source lines in accordance with the pixel voltages.
In the meantime, in some cases, the driver control circuit is provided with an operation setting unit which sets, e.g., a vertical scanning direction and a gamma correction amount. The operation setting unit is connected via a control bus to a processor, such as a microcomputer, disposed outside the liquid crystal display device. At present, an I2C bus, proposed by Philips, is prevailing as this control bus. For example, when a product inspection of the liquid crystal display device is conducted, the processor supplies various instruction data to the operation setting unit by a packet communication method, and the operation setting unit executes operation settings in accordance with the instruction data. In this case, the processor functions as a master of the operation setting unit, and the operation setting unit functions as a slave of the processor. In recent years, with versatility in operation settings, there has been an increasing need to provide the driver control circuit with an internal processor, which functions as a second master of the operation setting unit, in addition to the processor that is provided on the outside of the liquid crystal display device. Although the specifications of the I2C bus support a double master scheme in which two masters are provided for one slave, each of the masters needs to be configured to control the slave during a period in which the control bus is not occupied by the other master, in order to avoid collision of signals on the control bus. The control with this configuration, however, is based on the frequencies and phases of clock signals input to the respective masters, and is complex and difficult.